The present invention relates generally to a semiconductor circuit and more particularly to a family of high performance logic circuits.
Progress in computers and digital electronics constantly demands logic circuits that can manipulate digital signals at higher speed, lower signal levels and with less power consumption. Most such logic circuits are formed by combining simple building blocks such as gates and inverters.
FIG. 1 shows an inverter that uses NMOS transistors. F.sub.1 is a depletion-mode transistor and F.sub.3 is a zero-threshold transistor; both are placed in a conducting state by a zero or positive gate voltage. F.sub.2 and F.sub.4 are enhancement-mode transistors that are placed in a conducting state by a positive gate voltage.
When V.sub.i is at a high logic level, F.sub.2 and F.sub.4 will be conducting. This couples the ground potential to V.sub.j and V.sub.o, placing both F.sub.1 and F.sub.3 into a conducting state. With all four transistors conducting, significant currents flow through all the transistors. This leads to an undesirable amount of DC power consumption. Moreover, when V.sub.i is at a high logic level, the output voltage V.sub.o should be at the ground potential, but the actual value of V.sub.o depends on the ratio of the drain-to-source resistances through F.sub.3 and F.sub.4. This type of circuit is known as ratio design circuit.
FIG. 2 depicts a "ratioless" CMOS inverter circuit. When the input voltage V.sub.i is at a steady-state logic level (either high or low), the circuit will be in a stable condition and one of the two output transistors F.sub.5 and F.sub.6 will be in a non-conducting state. This results in much lower power consumption than in the circuit of FIG. 1. In addition, because one of the output transistors carries no significant current, the output voltage V.sub.o is either equal to zero or V.sub.1 depending on whether the input is high or low, respectively. Thus the output voltage swings all the way between the minimum and maximum power supply voltage. A drawback of the circuit is that it is relatively slow because the switching speed of the PMOS output transistor F.sub.5 is two or three times slower than the speed of the corresponding NMOS output transistor F.sub.3 in FIG. 1.
FIG. 3 shows a BiCMOS inverter in which the MOS pull-up and pull-down transistors F.sub.5 and F.sub.6 in FIG. 2 have been replaced with bipolar transistors F.sub.7 and F.sub.8. The logic levels of the circuit are still controlled by MOS transistors. Similar to the circuit in FIG. 2, only leakage current flows through the bipolar transistors when the inverter is in a stable condition. However, the bipolar transistors have greater current-handling capacity than the MOS output transistors and therefore they usually provide much faster switching speed when driving a capacitive load C.sub.L.
A drawback of the BiCMOS circuit is that the output voltage cannot swing all the way between the minimum and maximum power supply voltage. This is because a bipolar transistor has a minimum forward-bias diode-voltage drop that is determined by the material of the transistor; for silicon transistors, this forward voltage drop is about 0.7 volts. Thus, in the inverter circuit of FIG. 3, a low input voltage results in an output voltage of (V.sub.1 -0.7) rather than V.sub.1, and a high input voltage results in an output voltage of 0.7 volts rather than zero.
FIG. 4 shows a BiNMOS inverter circuit that is similar to the circuit shown in FIG. 3 except that the bipolar pull-down transistor F.sub.8 has been replaced with an NMOS transistor F.sub.10. The NMOS transistor does not have a forward-bias diode-voltage drop. Thus, in the circuit of FIG. 4 the output can go to zero with a "high" input. But, it still cannot go to a higher level than (V.sub.1 -0.7) with a "low" input.
The trend in modern circuit design, especially for hand-held and other battery-powered devices, is toward lower supply voltages. Because of the forward-bias diode-voltage drop that is inherent in a bipolar transistor, the circuits of FIGS. 3 and 4 cannot be scaled with the supply voltage. As the supply voltage decreases, the forward-bias diode-voltage drop becomes a larger percentage of the supply voltage. This reduces the relative range of the output voltage of the circuit and results in a correspondingly increased susceptibility to noise.
In addition, bipolar transistors are subject to saturation, which slows down the circuit. Also, the process technology required to manufacture a BiCMOS or BiNMOS circuit is more complex than that required to manufacture an MOS circuit; for example, at least four additional masks are required.
From the foregoing it will be apparent that there is a need for a logic circuit that offers the switching speed of bipolar transistors but that avoids the drawbacks of reduced voltage swing, manufacturing complexity, and slow recovery from inadvertent saturation.